IC Design and Verification Journal

On Demand

ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers (WHITE PAPER)

Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.

Sponsored by: EvE

Introducing Synphony High Level Synthesis (CHALK TALK)

Having difficulty getting complex algorithms into hardware? Join Amelia Dalton as she chats with Chris Eddington from Synopsys about the latest advances in high-level synthesis - going directly from Matlab into optimized hardware design.

Sponsored by: Synopsys

FPGA - PCB Co-Design Done The Right Way (CHALK TALK)

Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs.

Sponsored by: Cadence

Solving Today's Tough FPGA Design Problems (CHALK TALK)

Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today's more demanding FPGAs.

Sponsored by: Synopsys

Improving Software Development Productivity With Virtual Platforms (CHALK TALK)

Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms.

Sponsored by: Synopsys

Crossing the Gap between Algorithm and Hardware Implementation (CHALK TALK)

In this webcast Amelia Dalton will chat with Stuart Clubb of Mentor Graphics about how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. In this webcast, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types.

Sponsored by: Mentor Graphics

Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (WHITE PAPER)

Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices’ reprogrammability to validate hardware and software. Once the design is ready for volume production, designers are finding that certain types of ASICs—specifically, ASICs with a silicon platform and toolset that enable concurrent design with the FPGA, using identical I/Os, memory resources, and IP—help them meet power, performance, and cost targets.

Sponsored by: Altera

Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER)

Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence. This scheme introduces ownership attributes of local cache lines, which are posted throughout the cluster upon intent to use or change.

Sponsored by: MIPS

Billion Gate Emulation with ZeBu-Server (CHALK TALK)

Running out of verification capacity? Today's huge designs demand a new solution with dramatically improved speed, capacity, and flexibility. Join Amelia Dalton as she talks with Ron Choi of Eve about the challenges of Billion-Gate emulation.

Sponsored by: EvE

Catapult C Synthesis Designing a JPEG Compression Engine (CHALK TALK)

Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++.

Sponsored by: Mentor Graphics